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LTC2604/LTC2614/LTC2624 Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP
FEATURES
s
DESCRIPTIO
s s s s s s s s s
Smallest Pin Compatible Quad 16-Bit DAC: LTC2604: 16-Bits LTC2614: 14-Bits LTC2624: 12-Bits Guaranteed 16-Bit Monotonic Over Temperature Separate Reference Inputs for each DAC Wide 2.5V to 5.5V Supply Range Low Power Operation: 250A per DAC at 3V Individual DAC Power-Down to 1A, Max Ultralow Crosstalk Between DACs (<5V) High Rail-to-Rail Output Drive (15mA) Double Buffered Digital Inputs 16-Lead Narrow SSOP Package
The LTC(R)2604/LTC2614/LTC2624 are quad 16-,14- and 12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in 16-lead narrow SSOP packages. These parts have separate reference inputs for each DAC. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish advanced performance standards for output drive, crosstalk and load regulation in singlesupply, voltage output multiples. The parts use a simple SPI/MICROWIRETM compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisy-chain capability and a hardware CLR function are included. The LTC2604/LTC2614/LTC2624 incorporate a poweron reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after powerup, they stay at zero scale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corp.
APPLICATIO S
s s s s
Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRA
GND 1 REF LO 2 REF A 3 DAC REGISTER
VCC 16 REF D 15 INPUT REGISTER DAC REGISTER VOUT D DAC D 14
4
DAC A
INPUT REGISTER
VOUTA
INPUT REGISTER
DAC REGISTER
VOUT C 13 REF C 12 CLR 11 ERROR (LSB) DAC C
DAC REGISTER
VOUTB 5 REF B 6 CS/LD 7 SCK 8 DAC B
INPUT REGISTER
CONTROL LOGIC
DECODE
SDO 10 SDI 9
2604 BD
32-BIT SHIFT REGISTER
U
Differential Nonlinearity (LTC2604)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2604 TA01
W
U
VCC = 5V VREF = 4.096V
2604f
1
LTC2604/LTC2614/LTC2624 ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND REF LO REF A VOUT A VOUT B REF B CS/LD SCK 1 2 3 4 5 6 7 8 16 VCC 15 REF D 14 VOUT D 13 VOUT C 12 REF C 11 CLR 10 SDO 9 SDI
Any Pin to GND ........................................... - 0.3V to 6V Any Pin to VCC ............................................ - 6V to 0.3V Maximum Junction Temperature ......................... 125C Operating Temperature Range LTC2604/LTC2614/LTC2624C ............... 0C to 70C LTC2604/LTC2614/LTC2624I ............ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................ 300C
ORDER PART NUMBER LTC2604CGN LTC2604IGN LTC2614CGN LTC2614IGN LTC2624CGN LTC2624IGN GN PART MARKING 2604 2604I 2614 2614I 2624 2624I
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 150C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL Differential Nonlinearity INL Integral Nonlinearity Load Regulation CONDITIONS
q
MIN 12 12
LTC2624 TYP MAX
MIN 14 14
LTC2614 TYP MAX
MIN 16 16
LTC2604 TYP MAX
UNITS Bits Bits LSB LSB LSB/mA LSB/mA LSB/mA LSB/mA mV mV V/C %FSR ppm/C
(Note 2) (Note 2) (Note 2) VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.5V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking (Note 7)
q q q q q q q q q
0.9
0.5 4
4 0.1 0.1 0.2 0.2 1.5 1.5 5
1 16 0.5 0.5 1 1 9 9
14 0.3 0.3 0.7 0.7 1.5 1.5 5
1 64 2 2 4 4 9 9
0.025 0.125 0.025 0.125 0.05 0.05 1.5 1.5 5 0.25 0.25 9 9
ZSE VOS
GE
Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient
q
0.1 0.7 5
0.1 0.7 5
0.1 0.7 5
SYMBOL PSR ROUT
PARAMETER Power Supply Rejection DC Output Impedance
CONDITIONS VCC = 5V 10% VCC = 3V 10% VREF = VCC = 5V, Midscale; -15mA IOUT 15mA VREF = VCC = 2.5V, Midscale; -7.5mA IOUT 7.5mA
q q
LTC2604/LTC2614/LTC2624 MIN TYP MAX -80 -80 0.025 0.15 0.030 0.15
UNITS dB dB
2
U
2604f
W
U
U
WW
W
LTC2604/LTC2614/LTC2624
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER DC Crosstalk (Note 4) CONDITIONS Due to Full Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND VCC = 2.5V, VREF = 2.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND LTC2604/LTC2614/LTC2624 MIN TYP MAX 5 1 3.5
q q q q q
ELECTRICAL CHARACTERISTICS
UNITS V V/mA V mA mA mA mA V k pF A V mA mA A A V V V V V V A pF
ISC
Short-Circuit Output Current
15 15 7.5 7.5 0 88
34 36 18 24
60 60 50 50 VCC 160 1 5.5 2 1.6 1 1
Reference Input Input Voltage Range Resistance Capacitance IREF Reference Current, Power Down Mode Power Supply VCC Positive Supply Voltage ICC Supply Current
Normal Mode All DACs Powered Down For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V Load Current = -100A Load Current = +100A VIN = GND to VCC (Note 6) LTC2624 TYP MAX 7
q q q q q q q q q q q q q q q
128 14 0.001
2.5 1.3 1 0.35 0.10 2.4 2.0
Digital I/O VIH Digital Input High Voltage VIL VOH VOL ILK CIN Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance
0.8 0.6 VCC - 0.4 0.4 1 8 LTC2604 TYP MAX 7 9 10 2.7 4.8 5.2 0.80 1000 12 180 120 100 15
SYMBOL PARAMETER AC Performance ts Settling Time (Note 8)
CONDITIONS 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits)
MIN
MIN
LTC2614 TYP MAX 7 9 2.7 4.8 0.80 1000 12 180 120 100 15
MIN
UNITS s s s s s s V/s pF nV * s kHz nV/Hz nV/Hz VP-P
2604f
Settling Time for 1LSB Step (Note 9) Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth Output Voltage Noise Density Output Voltage Noise
2.7
At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz
en
0.80 1000 12 180 120 100 15
3
LTC2604/LTC2614/LTC2624
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted.
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V CONDITIONS
q q q q q q q q q q q
TI I G CHARACTERISTICS
VCC = 2.5V to 5.5V 4 4 9 9 10 7 7 20 45 20 7 50 ns ns ns ns ns ns ns ns ns ns ns MHz
t9 t10
Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256, linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at midscale, unless otherwise noted.
TYPICAL PERFOR A CE CHARACTERISTICS
Current Limiting
0.10 0.08 0.06 0.04 CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V
VOUT (mV)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 20 30 40 -1.0 -35 -25 -15 -5 5 IOUT (mA) 15 25 35 VREF = VCC = 3V VREF = VCC = 5V
OFFSET ERROR (mV)
VOUT (V)
0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 10 -40 -30 -20 -10 0 IOUT (mA) VREF = VCC = 3V VREF = VCC = 5V
4
UW
UW
LTC2604/LTC2614/LTC2624 MIN TYP MAX
UNITS
CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency 50% Duty Cycle
q
Note 5: RL = 2k to GND or VCC. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2604), code 64 (LTC2614) or code 16 (LTC2624), and at full scale. Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scate to 1/4 scale. Load is 2k in parallel with 200pF to GND. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between half scale and half scale -1. Load is 2k in parallel with 200pF to GND.
(LTC2604/LTC2614/LTC2624)
Load Regulation
1.0 0.8 0.6 2 1 0 -1 -2 CODE = MIDSCALE 3
Offset Error vs Temperature
-3 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2604 G01
2604 G02
2604 G03
2604f
LTC2604/LTC2614/LTC2624 TYPICAL PERFOR A CE CHARACTERISTICS
Zero-Scale Error vs Temperature
3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 -50 0.4 0.3 OFFSET ERROR (mV) -30 -10 10 30 50 TEMPERATURE (C) 70 90 0.2 0.1 0 -0.1 -0.2 -0.3 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -0.4 -50 -2 -3 2.5
Gain Error vs VCC
0.4 0.3 0.2
GAIN ERROR (%FSR) 450 400 350 300 ICC (nA) 250 200 150
0.1 0 -0.1 -0.2
-0.3 -0.4 2.5
3
3.5
4 VCC (V)
4.5
Midscale Glitch Impulse
VOUT 10mV/DIV 12nV-s TYP
VOUT (V)
CS/LD 5V/DIV
2604 G10
2.5s/DIV
UW
2604 G04
(LTC2604/LTC2614/LTC2624) Offset Error vs VCC
3 2 1 0 -1
Gain Error vs Temperature
3
3.5
4 VCC (V)
4.5
5
5.5
2604 G06
2604 G05
ICC Shutdown vs VCC
Large-Signal Settling
VOUT 0.5V/DIV
VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5s/DIV
2604 G09
100 50
5
5.5
2604 G07
0 2.5
3
3.5
4 VCC (V)
4.5
5
5.5
2604 G08
Power-On Reset Glitch
5.0 4.5 4.0
Headroom at Rails vs Output Current
5V SOURCING
VCC 1V/DIV 4mV PEAK 4mV PEAK VOUT 10mV/DIV 250s/DIV
2604 G11
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 456 IOUT (mA) 7 8 9 10 3V SINKING 5V SINKING 3V SOURCING
2604 G12
2604f
5
LTC2604/LTC2614/LTC2624 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Logic Voltage
2.4 2.3 2.2 2.1 ICC (mA) 2.0 1.9 1.8 1.7
2.5s/DIV
2604 G14
VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC
1.6 1.5 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5
Multiplying Frequency Response
0 -3 -6 -9 -12 -15
10mA/DIV
dB
-18 -21 -24 -27 -30 -33 -36 1k VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 10k 100k FREQUENCY (Hz) 1M
2604 G16
10mA/DIV
6
UW
2604 G13
(LTC2604/LTC2614/LTC2624) Hardware CLR
Exiting Power-Down to Midscale
VCC = 5V VREF = 2V VOUT 0.5V/DIV DACs A-C IN POWER-DOWN MODE CS/LD 5V/DIV
VOUT 1V/DIV
CLR 5V/DIV 1s/DIV
2604 G15
Output Voltage Noise, 0.1Hz to 10Hz
Short-Circuit Output Current vs VOUT (Sinking)
VOUT 10V/DIV
0mA
0
1
2
3
456 SECONDS
7
8
9
10
VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 1V/DIV
2604 G18
2604 G17
Short-Circuit Output Current vs VOUT (Sourcing)
0mA
VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 1V/DIV
2604 G19
2604f
LTC2604/LTC2614/LTC2624 TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
32 24 16 DNL (LSB) INL (LSB) 8 0 -8 -16 -24 -32 0 16384 32768 CODE 49152 65535
2604 G20
VCC = 5V VREF = 4.096V
INL (LSB)
DNL vs Temperature
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -16 -0.6 -0.8 -1.0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -24 -32 DNL (NEG) VCC = 5V VREF = 4.096V DNL (POS) INL (LSB) 32 24 16
0 -8 INL (NEG)
DNL (LSB)
Settling to 1LSB
VOUT 100V/DIV 9.7s CS/LD 2V/DIV
VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
UW
2604 G23
(LTC2604) INL vs Temperature
32 24 16 8 0 -8 -16 -24 INL (NEG) INL (POS) VCC = 5V VREF = 4.096V
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2604 G21
VCC = 5V VREF = 4.096V
-32 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2604 G22
INL vs VREF
1.5 VCC = 5.5V 1.0 INL (POS) 0.5
DNL vs VREF
VCC = 5.5V
8
DNL (POS) 0 DNL (NEG) -0.5 -1.0 -1.5
0
1
2 3 VREF (V)
4
5
2604 G24
0
1
2 3 VREF (V)
4
5
2604 G25
Settling of Full-Scale Step
VOUT 100V/DIV
12.3s
CS/LD 2V/DIV
2s/DIV
2604 G26
5s/DIV VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS SETTLING TO 1LSB
2604 G27
2604f
7
LTC2604/LTC2614/LTC2624 TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2614)
Integral Nonlinearity (INL)
8 6 4 0.4 DNL (LSB) INL (LSB) 2 0 -2 -4 -0.6 -6 -8 0 4096 8192 CODE 12288 16383
2604 G28
VCC = 5V VREF = 4.096V
(LTC2624)
Integral Nonlinearity (INL)
2.0 1.5 1.0 0.4 DNL (LSB) INL (LSB) 0.5 0 -0.5 -1.0 -0.6 -1.5 -2.0 0 1024 2048 CODE 3072 4095
2604 G31
VCC = 5V VREF = 4.096V
PIN FUNCTIONS
GND (Pin 1): Analog Ground. REF LO (Pin 2): Reference Low. The voltage at this pin sets the zero scale (ZS) voltage of all DACs. The voltage range is 0 REF LO VCC - 2.5V. REF A, REF B, REF C, REF D (Pins 3, 6, 12, 15): Reference Voltage Inputs for each DAC. REF x sets the full scale voltage of the DACs. 0V REF x VCC. VOUT A to VOUT D (Pins 4, 5, 13, 14): DAC Analog Voltage Outputs. The output range is from REF LO to REF x. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2604/LTC2614/LTC2624 accepts input word lengths of either 24 or 32 bits.
2604f
8
UW
Differential Nonlinearity (DNL)
1.0 0.8 0.6
VOUT 100V/DIV
Settling to 1LSB
VCC = 5V VREF = 4.096V
0.2 0 -0.2 -0.4
CS/LD 2V/DIV
8.9s 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2604 G30
-0.8 -1.0 0 4096 8192 CODE 12288 16383
2604 G29
Differential Nonlinearity (DNL)
1.0 0.8 0.6 VCC = 5V VREF = 4.096V
Settling to 1LSB
6.8s VOUT 1mV/DIV
0.2 0 -0.2 -0.4
CS/LD 2V/DIV
2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2604 G33
-0.8 -1.0 0 1024 2048 CODE 3072 4095
2604 G32
U
U
U
LTC2604/LTC2614/LTC2624
PIN FUNCTIONS
SDO (Pin 10): Serial Interface Data Output. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is used for daisy-chain operation. CLR (Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V. CMOS and TTLcompatible. VCC (Pin 16): Supply Voltage Input. 2.5V VCC 5.5V.
BLOCK DIAGRA
GND 1 REF LO 2 REF A 3
INPUT REGISTER
DAC REGISTER
DAC REGISTER
4
DAC A
INPUT REGISTER
VOUTA
INPUT REGISTER
DAC REGISTER
DAC REGISTER
VOUTB 5 REF B 6 CS/LD 7 SCK 8 DAC B
INPUT REGISTER
TI I G DIAGRA
SCK
SDI t5 CS/LD t8 SDO
2604 F01
W
W
U
U
UW
U
VCC 16 REF D 15 VOUT D DAC D 14
VOUT C DAC C 13 REF C 12 CLR 11
CONTROL LOGIC
DECODE
SDO 10 SDI 9
2604 BD
32-BIT SHIFT REGISTER
t1 t2 1 t3 2 t4 3 23 t6 24 t10
t7
Figure 1
2604f
9
LTC2604/LTC2614/LTC2624
OPERATIO
Power-On Reset
The LTC2604/LTC2614/LTC2624 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2604/ LTC2614/LTC2624 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pins 3, 6, 12 and 15) should be kept within the range - 0.3V REF x VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The digital-to-analog transfer function is k VOUT(IDEAL) = N [REF x - REFLO] + REFLO 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution and REF x is the voltage at REF A, REF B, REF C and REF D (Pins 3, 6, 12 and 15). Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering-on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don't-care bits (LTC2604, LTC2614 and LTC2624 respectively). Data can
10
U
Table 1.
COMMAND* C3 C2 C1 C0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power Up) n Power Down n No Operation ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 DAC A DAC B DAC C DAC D All DACs
*Command and address codes not shown are reserved and should not be used.
only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the block diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don't-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the 32-bit sequence. The 32-bit word is required for daisychain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes).
2604f
LTC2604/LTC2614/LTC2624
OPERATIO
INPUT WORD (LTC2604)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (16 BITS) D15 D14 D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2604 TBL01
INPUT WORD (LTC2614)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 DATA (14 BITS + 2 DON'T-CARE BITS) D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2604 TBL02
INPUT WORD (LTC2624)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D11 D10 D9 MSB DATA (12 BITS + 4 DON'T-CARE BITS) D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB
2604 TBL03
Daisy-Chain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a "daisy chain" series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain.
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X X
X X X X
Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four outputs are needed. When in power-down, the buffer amplifiers, bias circuits and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 90k resistors. Input- and DAC-register contents are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply current is reduced by approximately 1/4 for each DAC powered down. The effective resistance at REF x (pins 3, 6, 12 and 15) are at highimpedance input (typically > 1G) when the corresponding DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is 5s. If on the
2604f
11
LTC2604/LTC2614/LTC2624
OPERATIO
other hand, all four DACs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power up delay time is 12s (for VCC = 5V) or 30s (for VCC = 3V). Voltage Outputs Each of the four rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.025 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30 * 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separate.
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The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin functions as a return path for power supply currents in the device and should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. When a zero scale DAC output voltage of zero is desired, the REFLO pin (pin 2) should be connected to system star ground. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pins are tied to VCC. If REF x = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No fullscale limiting can occur if REF x is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
2604f
OPERATIO
SCK 2 7 17 D7
2604 F02a
1 10 13 D11 DATA WORD D10 D9 D8 D6 D5 D4 D3 D2 D1 D0 14 21 23 D14 D13 D12 11 12 18 24 16 20 22 C1 ADDRESS WORD C0 A3 A2 A1 A0 D15
3 4 5 6 8 9 15 19
SDI
C3
C2
COMMAND WORD
24-BIT INPUT WORD
Figure 2a. LTC2604 24-Bit Load Sequence (Minimum Input Word) LTC2614 SDI Data Word: 14-Bit Input Code + 2 Don't Care Bits LTC2624 SDI Data Word: 12-Bit Input Code + 4 Don't Care Bits
CS/LD 6 7 14 17 D15 D14 D13 D12 D11 D10 A2 ADDRESS WORD C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 A1 A0 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 A3 8 9 10 13 21 11 12 18 16 20 22 15 19 X 23 D9 24 D8 25 D7 DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
SDO
X
X
X
X
X
PREVIOUS 32-BIT INPUT WORD t1 t2 SCK 17 t3 SDI SDO D15 t8 PREVIOUS D15 PREVIOUS D14 t4 D14 18
CURRENT 32-BIT INPUT WORD
2604 F02b
Figure 2b. LTC2604 32-Bit Load Sequence LTC2614 SDI/SDO Data Word: 14-Bit Input Code + 2 Don't Care Bits LTC2624 SDI/SDO Data Word: 12-Bit Input Code + 4 Don't Care Bits
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LTC2604/LTC2614/LTC2624
CS/LD
13
2604f
LTC2604/LTC2614/LTC2624
OPERATIO
OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) 65, 535
0V NEGATIVE OFFSET INPUT CODE (b)
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
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VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c)
2604 F03
2604f
LTC2604/LTC2614/LTC2624
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .0532 - .0688 (1.35 - 1.75) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 BSC .008 - .012 (0.203 - 0.305) TYP .0250 (0.635) BSC
GN16 (SSOP) 0204
2604f
15
LTC2604/LTC2614/LTC2624
TYPICAL APPLICATIO
70MHz IN 47pF ZC830 49.9 20pF 49.9 10pF
5V 2.74k 1% LO 100k 100k
2.74k 1%
Q INPUT 5V 2.74k 1% 2.74k 1% *ZETEX (516) 543-7100
Figure 4. Using DAC A and DAC B for Nearly Continuous Attenuation Control and DAC C and DAC D to Trim for Minimum LO Feedthrough in a Mixer.
RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 LTC2600/LTC2610/LTC2620 LTC2602/LTC2612/LTC2622 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5s/750A, 8s/450A VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2s for 10V Step 250A per DAC, 2.5V to 5.5V Supply Range 300A per DAC, 2.5V to 5.5V Supply Range
2604f LT/TP 0304 1K * PRINTED IN THE USA
16 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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5V 1k 10k 0.1F 10k 0.01F 20 0.1F 10k 49.9 0.01F OUT 5V 1k 10k ZC830 DAC A OPTIONAL DAC C 20k 0.1F CS/LD SCK SDI LTC2604 5V 2.74k 1% DAC D 20k 0.1F DAC B OPTIONAL 90 2.74k 1% I+Q MODULATOR 5V 0 2.74k 1% 2.74k 1%
2604 F04
I INPUT
RF
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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